NPTEL Computer Architecture And Organization Assignment 10 Answer

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1 point

Which of the following is/are not true for DMA data transfer?

a.Data are transferred directly between the memory and the peripheral without CPU intervention.

b.CPU puts all its memory bus lines in a high impedance state before data transfer can begin.

c.It is more suitable for devices where the data transfer rates vary widely.

d.None of these.

Ans  – B

1 point

Programmed I/O is not suitable for high-speed data transfer because:

a.To transfer every word between the I/O device and memory, a set of machine instructions has to be executed.

b.It does not support the synchronous data transmission mode that is required for many high-speed peripherals like the disk.

c.A lot of CPU time is wasted.

d.None of these.

Ans  –  C

Suppose that a disk is rotating at a speed of 10,000 rpm, and 120 Kbytes of data are recorded in every track. Once the disk head reaches the desired track, the sustained data transfer rate will be ……………… Mbytes/sec.

1 point

On a non-pipelined sequential processor, the following program segment, that is part of the Interrupt Service Routine (ISR), is given to transfer 500 bytes from an I/O device to memory.

Initialize the memory address register 

Initialize word count register to 500 

Loop:    Load a byte from the device

    Store in the memory at address given by the address register

Increment the memory address register

Decrement the word count register

If count != 0 goto Loop

Assume that each statement in the program is equivalent to a machine instruction that takes one clock cycle to execute if it is a non-LOAD/STORE instruction. The LOAD/STORE instructions take two clock cycles to execute.

The system designer also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.

The approximate speedup when the DMA controller-based design is used in place of the interrupt-driven approach is ………………….

Ans  – 1

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1 point

Consider a programmed I/O system where 35 instructions are required to be executed for the transfer of each word of data. The cycles-per-instruction (CPI) of the machine is 1.3, and the processor clock frequency is 1.5 GHz. The maximum data transfer rate will be ___________ million words per second. (Assume 1 million = 106)

Ans  –  106

1 point

1 point

The maximum data transfer rate in direct memory access (DMA) transfer depends on:

a.The processor clock frequency.

b.Access time of main memory.

c.Number of instructions required to transfer a word from an I/O device to memory, or vice versa.

d.Average cycles per instruction (CPI).

Ans  –  B

1 point

a.The DMA controller has three internal registers (word count, memory address, and disk address) that are shared among the four channels.

b.The interrupt request (INTR) signal is activated after the transfer of every word.

c.When an I/O device requests for DMA transfer, the DMA controller activates the DMA-RQ line.

d.The CPU activates the DMA-ACK line after the DMA transfer is complete.

e.The CPU activates the DMA-ACK line after the CPU has relinquished control of the memory bus.

Ans  –  C

1 point

Consider a matrix keyboard consisting of 48 keys, organized as 8 rows and 6 columns. How many port lines will be required to interface the keyboard?

a.48

b.14

c.8

d.2

Ans  –  B

1 point

If we apply bit stuffing on the bit stream 100011111110011111101, the output bit stream will be:

a.10001111101100111110101

b.1000111111010011111101

c.10001111111000111111001

d.None of these.

Ans  –  B

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1 point

The maximum data transfer rates supported by USB 3.0 and USB 3.1 standards are respectively:

a.5 Mbits/sec and 10 Mbits/sec

b.5 Gbits/sec and 10 Gbits/sec

c.5 Gbytes/sec and 10 Gbytes/sec

d.None of these.

Ans  –  A