NPTEL Computer Architecture And Organization Assignment 2 Answer

We Discuss About That NPTEL Computer Architecture And Organization Assignment 2 Answer

NPTEL Computer Architecture And Organization Assignment 2 Answer – Here All The Questions and Answers Provided to Help All The Students and NPTEL Candidate as a Reference Purpose, It is Mandetory to Submit Your Weekly Assignment By Your Own Understand Level.

Are you looking for the Assignment Answers to NPTEL Computer Architecture And Organization Assignment 2 Answer? If Yes You are in Our Great Place to Getting Your Solution, This Post Should be help you with the Assignment answer to the National Programme on Technology Enhanced Learning (NPTEL) Course “NPTEL Computer Architecture And Organization Assignment 2 Answer”

NPTEL Computer Architecture And Organization Assignment

Next Week Assignment Answers

CHECK HERE OTHERS NPTEL ASSIGNMENTS ANSWERS 

BELOW YOU CAN GET YOUR NPTEL Computer Architecture And Organization Assignment 2 Answer 2022? :

Answers will be Uploaded Shortly and it will be Notified on Telegram, So JOIN NOW

1 point

The decimal number (99.5)10(99.5)10 in binary notation is:

 a.1000011.1

 b.1100011.1

 c.0101010.1

 d.1110011.1

ans -b

1 point

The hexadecimal number (6A.4)16(6A.4)16 in binary notation is:

 a.1101100.01

 b.1101101.10

 c.1101010.01

 d.1101010.10

ans – c

1 point

What are the maximum and minimum numbers that can be represented in 1’s complement using 8-bits:

 a.+128 and -128

 b.+127 and -127

 c.+126 and -126

 d.+128 and -126

ans – b

1 point

Which of the following is not an advantage of 2’s complement representation?

 a.Unique representation of zero

 b.Subtraction can be done using addition

 c.Efficient circuitry

 d.Expensive circuitry

ans – d

Answers will be Uploaded Shortly and it will be Notified on Telegram, So JOIN NOW

1 point

The addressing mode that adds the displacement and the index register to get the effective address of the operand is:

 a.Indexed addressing

 b.Base-Indexed addressing

 c.Register Indirect addressing

 d.Relative addressing

ans –  b

1 point

Register R1 and R2 contain values 100 and 1000 respectively in decimal, and the word length of the processor is 32 bits. What will be the value of the effective address of the memory operand for the instruction “STORE R3, 70(R1, R2)?”

 a.1132

 b.1170

 c.1100

 d.1202

ans – b

1 point

Given a sequence of instruction: 

ADD     R1,R2,R3

SUB     R4,R5,R6

MOV     R4,R7

Identify the addressing mode used in the instructions.

 a.Direct addressing

 b.Indirect addressing

 c.Register addressing

 d.Register indirect addressing

ans –  b

1 point

What is the equivalent MIPS32 instruction for the C code segment:

Answers will be Uploaded Shortly and it will be Notified on Telegram, So JOIN NOW

A = B + C;

F = A + D – E;

Assume that the variable values are loaded in appropriate registers.

 a.Add $s0, $s1, $s2
Add $t1, $s0, $s3
Sub $s5, $t1, $s4

 b. Add $s0, $s1, $s2
Add $t1, $s1, $s3
Sub $s5, $t1, $s4

 c. Add $s0, $s1, $s2
Add $t1, $s3, $s0
Sub $s5, $t2, $s1

 d. Add $s0, $s1, $s2
Add $t1, $s1, $s0
Sub $s5, $t2, $s1

ans – a

1 point

The MIPS instruction SLA $S1, $S2, 6 means:

 a.Shift left $S1 by 6 places, and store it in $S2

 b.Shift left $S2 by 6 places, and add it with $S1

 c.Shift left $S1 by 6 places, and add it with $S2

 d.Shift left $S2 by 6 places, and store it in $S1

ans – d

1 point

Which of the following is false in regards to the assembler directive of the MIPS32 assembly code?

 a..text – Specifies the user text segment

 b..space n – Reserve space for n non-sequential bytes in memory

 c. .ascii str – Stores the specified string in memory in ASCII code

 d. .globl gbl – Specifies that the symbol ‘gbl’ is global

ans – d

Yhaa You have done it but next? if YOU Want to your Others NPTEL Computer Architecture And Organization Assignment 2 Answer  Then Follow US HERE and Join Telegram.