NPTEL Computer Architecture And Organization Assignment 8 Answer

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1 point

The binary fraction 11000001.101 represents the decimal number 193.625. What will its value be if the fraction point is shifted by six positions to get the number 11.000001101?

 a.The value will get divided by 64

 b.The value will get multiplied by 64

 c.The value will be 3.025390625

 d.The value will be 12392

Ans  – C,D

1 point

Which of the following decimal fractions can be represented precisely in binary?

 a.85/128

 b.54/96

 c.33/99

 d.100/500

 e.500/800

 f. 3/2048

Ans  –  D

1 point

For single-precision floating-point number representation using IEEE-754 format, which of the following statements is false?

 a.There is a separate bit to store the sign of the number.

 b.The mantissa is a fraction generally in the range of 1.0 to 2.0.

 c.The exponent is expressed in biased notation.

 d.None of these.

Ans  –  C

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1 point

For a floating-point representation with 64 bits in the mantissa and 12 bits in the exponent, the number of significant digits in decimal and the maximum (positive) value of the exponent in decimal will be:

 a.15 and 48

 b.20 and 617

 c.19 and 616

 d.7 and 38

Ans  –  C

1 point

What is the purpose of mantissa alignment during floating-point addition?

 a.To make the exponents equal so that the mantissa values can be directly added.

 b.To increase the accuracy of the final result.

 c.To make the number of significant digits in the two mantissa values to be added as close as possible.

 d.None of these.

Ans  –  C

If 16 bits are used to represent the exponent of a floating-point number, the maximum exponent value that can be represented in decimal (i.e., the value y for 10y10y) will be _______.

Ans  –  64

1 point

1 point

Consider a 6-stage pipeline with stage delays of 35, 40, 25, 50, 45, and 20 nanoseconds, respectively. The delay of each latch stage is 5 nanoseconds. What will be the total time required to process 2500 sets of data in the pipeline?

 a.137.775 microseconds

 b.125.25 microseconds

 c.537.5 microseconds

 d.612.5 microseconds

Ans  –  C

1 point

 a.3

 b.4

 c.5

 d.6

 e.7

Ans  –  D,C,E

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1 point

For an n-stage pipeline implementation of some computation, the maximum speedup that can be obtained is upper bounded by:

 a.2n

 b.n

c. 2n2n

 d.None of the above

Ans  –  A

1 point

Consider a pipelined processor, where the inter-stage pipeline registers are assumed to be of zero latency, and the stage delays are specified in nanoseconds. Which of the following will have the highest clock frequency?

 a.4-stage pipeline with stage delays 1, 2, 2 and 1

 b.4-stage pipeline with stage delays 1, 1.5, 1.5, and 1.5

 c.5-stage pipeline with stage delays 0.5, 1, 1, 0.6 and 1

 d.5-stage pipeline with stage delays 0.5, 0.5, 0.3, 1 and 1.1

Ans  –  B

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